Hardware Chip Performance of CORDIC Based OFDM Transceiver for Wireless Communication

The fourth-generation (4G) and fifth-generation (5G) wireless communication systems use the orthogonal frequency division multiplexing (OFDM) modulation techniques subcarrier allocations. OFDM modulator demodulator have inverse fast Fourier transform (IFFT) (FFT) respectively. biggest challenge in IFFT/FFT processor is computation of imaginary real values. CORDIC has been proved one best rotation algorithms for logarithmic, trigonometric, complex calculations. proposed work focuses on transceiver hardware chip implementation, which 8-point to 1024-point IFFT FFT are used compute operations transmitter receiver coordinate digital computer (CORDIC) algorithm read-only memory (ROM)-based architecture store twiddle factors their angle generators. address generation unit required fetch data write results into appropriate sequence. provides low memory, delay, optimized field-programmable gate array (FPGA) comparison normal system. comparative performance CORDIC-FFT based estimated using FPGA parameters: slices, flip-flops, lookup table (LUTs), frequency, power, delay. design developed integrated synthesis environment (ISE) Xilinx version 14.7 software, synthesized very-high-speed circuit description language (VHDL), tested Virtex-5 FPGA.